The sample and hold circuit, as its name implies, samples an input signal and holds on its last sampled value until the input is sampled again.
Figure shows the Circuit Diagram of a SAMPLE AND HOLD Circuit using 741 OP AMP with an E-MOSFET. In this circuit the E-MOSFET works as a switch that is controlled by the sample-and-hold control voltage Vs, and the capacitor C serves as a storage element.
The analog signal Vin to be sampled is applied to the drain, and sample and hold control voltage Vs is applied to the gate of the E-MOSFET. During the Positive portion of Vs, the E-mosfet conducts and act as a closed switch. This allows input voltage to charge capacitor C. In other words input voltage appears across C and in turn at the output, as shown in figure below-
On the other hand, when Vs is zero the E-mosfet is off (Non conductive) and acts as an open switch. The only discharge path for C is, therefore, through the operational amplifier (OP AMP). However, the input resistance of the op amp voltage follower is also very high; hence the voltage across C is retained. The time periods Ts of the sample and hold control voltage Vs during which the voltage across the capacitor is equal to the input voltage are called sample periods. The time period Th of Vs during which the voltage across the capacitor is constant are called hold periods. The output of the OP-AMP is usually processed/observed during hold periods. To obtain close approximation of the input wave form, the frequency of the sample and hold control voltage must be significantly higher than that of the input. In critical applications a precision or high speed op amp is helpful. If possible choose a low-leakage capacitor made of material such as teflon or polyethylene.
A significant reduction in size and improved performance can be achieved by using a specially designed sample and hold IC such as the LF398. The sample and hold circuit is commonly used in digital interfacing and communications such as analog to digital and pulse modulation systems.
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Figure shows the Circuit Diagram of a SAMPLE AND HOLD Circuit using 741 OP AMP with an E-MOSFET. In this circuit the E-MOSFET works as a switch that is controlled by the sample-and-hold control voltage Vs, and the capacitor C serves as a storage element.
CIRCUIT OPERATION OF SAMPLE AND HOLD
The analog signal Vin to be sampled is applied to the drain, and sample and hold control voltage Vs is applied to the gate of the E-MOSFET. During the Positive portion of Vs, the E-mosfet conducts and act as a closed switch. This allows input voltage to charge capacitor C. In other words input voltage appears across C and in turn at the output, as shown in figure below-
On the other hand, when Vs is zero the E-mosfet is off (Non conductive) and acts as an open switch. The only discharge path for C is, therefore, through the operational amplifier (OP AMP). However, the input resistance of the op amp voltage follower is also very high; hence the voltage across C is retained. The time periods Ts of the sample and hold control voltage Vs during which the voltage across the capacitor is equal to the input voltage are called sample periods. The time period Th of Vs during which the voltage across the capacitor is constant are called hold periods. The output of the OP-AMP is usually processed/observed during hold periods. To obtain close approximation of the input wave form, the frequency of the sample and hold control voltage must be significantly higher than that of the input. In critical applications a precision or high speed op amp is helpful. If possible choose a low-leakage capacitor made of material such as teflon or polyethylene.
A significant reduction in size and improved performance can be achieved by using a specially designed sample and hold IC such as the LF398. The sample and hold circuit is commonly used in digital interfacing and communications such as analog to digital and pulse modulation systems.
You may also like:-ZERO CROSSING DETECTOR USING OP AMP
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